1. Field of the Invention
This invention relates generally to data processing systems, and more particularly, to a method and apparatus for providing a corrected data group to a destination circuitry.
2. Description of the Prior Art
As is well known in the art, various components of data processing systems must communicate. Various errors, for example, caused by the presence of noise or equipment failure can occur. Thus, incorrect data groups can be transmitted between various components of the data processing system. For example, data processing systems generally utilize signals corresponding to a high level and a low level state. Noise or equipment faults can cause a high state to be received when a low state was, in fact, transmitted.
A data group or word group consists of a plurality of high and low levels, which are generally referred to as "1" and "0", respectively. For example, the three bit word "101" correctly represents the quantity 5. If an error occurs during transmission, the code group can be received as "100", which is the quantity 4. Various codes were developed to allow both the detection and correction of errors.
It is known in the art to employ error detection and correction apparatus to check and correct the data supplied from the main memory for distribution to other components, such as the central processing unit of the data processing system.
In general, the error detection and correction apparatus was employed to correct errors prior to the data group being presented to the central processing unit. An example of this type of apparatus is shown in the U.S. Pat. No. 4,058,851 issued to Scheuneman on Nov. 15, 1977 and entitled "Conditional By-Pass of Error Correction for Dual Memory Access Time Selection". Scheuneman shows and describes a system wherein the main memory provides each data group read to both an error correction apparatus and an interface register. If the error can be corrected, the requestor, such as the central processing unit, is notified and the data group is again read from the memory. The output of the error correction apparatus, if the error correction apparatus indicates that the error is correctable, is supplied to the interface register and finally, to the requestor such as the central processing unit. Thus, the uncorrected data which contains an error is not transmitted to the requesting unit. The requesting unit must again address that data group within the main memory and then receive the corrected data.
It is also known to apply the data group from the memory to a data switch and to an error detection and correction circuitry. The data switch then selects either the data group from the memory or the corrected data group from the error detection and correction circuitry. Another type of system is shown generally in U.S. patent application Ser. No. 930,965 by Suelflow et al, now abandoned. As the speed of operation of the various components of the data processing system increase, it is desirable that the data not be delayed during the time the error and correction circuitry is performing its function.
None of the constructions shown in the prior art show and describe apparatus for supplying a corrected data group from a memory to a destination circuitry which allows the uncorrected data to continue on to the destination circuitry through a data switch and the corrected data group along with subsequent data groups being received from the error correction and detection circuitry through the data switch.